Intel Shipping Stratix 10

Stratix 10 DX FPGAs with the new interfaces include the option to support select Intel Optane DC persistent memory DIMMs. They  increase bandwidth and provide coherent memory expansion and hardware acceleration for Xeon Scalable processors.

Data centre customers increasingly use hardware accelerators, like FPGAs, when more computational speed is required from server systems running networking and cloud-based applications such as AI training/inferencing or database-related workloads.

The effective performance of hardware accelerators depends heavily on the communications bandwidth and latency between one or more server CPUs, available system memory and any attached accelerator (GPU, FPGA, application-specific standard products, etc.).

By diverting certain tasks to accelerators, more CPU cores become available to work on other higher priority workloads, increasing data centre operator efficiency. Intel’s FPGA-based accelerators provide hardware-assisted performance combined with the flexibility to adapt to multiple workloads.

The UPI interface in combination with future select Intel Xeon Scalable Processors is claimed to deliver 37% lower latency and improve overall system performance via coherent data movement and a theoretical peak transfer rate of 28 GB/second. Memory coherent FPGA interfaces are a part of Intel’s roadmap as it moves toward Compute Express Link availability in 2021.

The  PCI-SIG compliant Gen4 x16 interface delivers a theoretical peak data bandwidth of 32 GB/second. Both data centre and non-data centre applications will realize about two times more throughput.

The memory controller supports up to eight Intel Optane DC persistent memory DIMMs per FPGA (up to 4 TB of non-volatile memory).

Other existing Stratix 10 FPGA features include 100 GB/second Ethernet, HBM2 memory stacks and a quad-core ARM Cortex-A53 processor subsystem with peripherals.