HBM2E Interface

Rambus has announced an interface  for HBM2E memory consisting of co-verified PHY and memory controller.

Operating at a top speed of 3.2 Gbps over a 1024-bit wide interface, the interface can deliver 410 GB/s of bandwidth with a single HBM2E DRAM stack.

In addition to the speed jump from 2.0 to 3.2 Gbps for HBM2E vs. HBM2, this latest iteration of the HBM standard now supports 12-high DRAM stacks of up to 24 Gb devices, providing an aggregate stack capacity of 36 GB.

With 3D stacking of memory, HBM2E provides high bandwidth and high capacity at low power and low latency in a very small footprint.

Both PHY and controller are fully compliant with the JEDEC JESD235B standard and are backward compatible to HBM2. While together they are a complete solution, both PHY and controller can be paired with JESD235B-compliant 3^rd-party solutions if so desired.