AFE7769D

Quad-channel RF transceiver with dual feedback paths and integrated CFR/DPD

The AFE77xxD is a pin-compatible family of high-performance, multichannel transceivers, integrating four (AFE7768D/AFE7769D) or two (AFE7728D) direct up-conversion transmitter chains, four (AFE7768D/AFE7769D) or two (AFE7728D) direct down-conversion receiver chains, two wideband RF sampling digitizing auxiliary chains (feedback paths) and low-power Digital Pre-Distortion (DPD) engine for Power Amplifier (PA) linearization. The high dynamic range of the transmitter and receiver chains enables wireless base stations to transmit and receive 2G, 3G, 4G, and 5G signals. The integrated Crest Factor Reduction (CFR) unit helps reduce the Peak-to-Average Ratio (PAR) of the input signal for more efficient transmission through the Power Amplifier. The integrated hardware accelerated DPD estimator and corrector provides flexible and efficient DPD solution for PA linearization. The integrated DPD engine corrects the distortion due to PA nonlinearity for signals up to 200MHz (AFE77x8D) / 300MHz (AFE7769D) instantaneous bandwidth, and within up to 650MHz (AFE77x8D) / 730MHz (AFE7769D) DPD expanded bandwidth. A dedicated GaN corrector addresses the long-term nonlinear memory effects due to charge trapping of GaN PAs.

The low power dissipation and high density channel integration of the AFE77xxD allow the device to address the power and size constraints of 4G and 5G base stations. The wideband and high dynamic range feedback path can assist the DPD of the power amplifiers in the transmitter chain through smart data capture at various intercepting points. The available 29.5Gbps SerDes speed can help reduce the number of lanes required to transfer the data in and out of the device.

Each receiver chain of the AFE77xxD includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated antialiasing low pass filters with programmable bandwidth, driving continuous-time sigma-delta ADCs. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz (AFE77x8D) / 300 MHz (AFE7769D). Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.

Each transmitter chain includes two 14-bit, 3.3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.

Each FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3.3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. The FB path integrates two independent NCOs, which allow for a fast switching between two observed RF input bands.

The synthesizer section integrates four fractional-N RF PLLs that can generate four different RF LOs, allowing the device to support up to two different bands, each one configured as two transmitters, two receivers, and one feedback path (with AFE7768D/AFE7769D), or one transmitter, one receiver, and one feedback path (with AFE7728D) .

• Quad (AFE776xD) / Dual (AFE7728D) transmitters based on 0-IF up-conversion architecture:

  • Up to 650 MHz (AFE77x8D) / 730 MHz (AFE7769D) of RF transmitted DPD expansion bandwidth per chain

• Quad (AFE776xD) / Dual (AFE7728D) receivers based on 0-IF down-conversion architecture:

  • Up to 200 MHz (AFE77x8D) / 300 MHz (AFE7769D) of RF received bandwidth per chain

• Feedback chain based on direct RF sampling architecture:

  • Up to 650 MHz (AFE77x8D) / 730 MHz (AFE7769D) of RF observed DPD expansion bandwidth

• Integrated CFR/DPD for PA linearization

  • Up to 200MHz (AFE77x8D) / 300MHz (AFE7769D) instantaneous bandwidth

  • Up to 650MHz (AFE77x8D) / 730MHz (AFE7769D) DPD expansion bandwidth

• Integrated CFR/DPD for PA linearization

  • Multistage CFR with configurable cancelling pulses

  • Hardware accelerated DPD estimation engine

  • Signal Dynamics based corrector for GaN PA linearization

  • Smart data capture

• RF frequency range: 600 MHz to 6 GHz

• Four wideband fractional-N PLL, VCO for TX and RX LO

• Dedicated integer-N PLL, VCO for data converters clock generation

• JESD204B and JESD204C SerDes interface support:

  • 4 SerDes transceivers up to 29.5 Gbps

  • 8b/10b and 64b/66b encoding

  • 16-bit, 12-bit, 24-bit and 32-bit formatting

  • Subclass 1 multi-device synchronization

• Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch

Number of TXs and RXs4 TXNumber of DUCs per TX4Number of DDCs per RX4RF frequency (max) (MHz)6000RF frequency (min) (MHz)600Operating temperature range (°C)-40 to 85RatingCatalog